Search - fir vhdl

[Other] m_cov_cul03_unmodule_precise

Description: 该程序用以对m序列码的调制在负dB情况下解调的仿真，是对基带信号的调制-procedures for the right sequence code m in the negative dB modulation of the demodulation simulation of the base band signal modulation
Platform: | Size: 1024 | Author: 孙晓东 | Hits:

[Communication-Mobile] 2005612300003FIRVHDL

Description: 自己在一个通信项目中设计的滤波器，在传统设计的基础上作了改进，具有更好的特性。-himself in a communications projects designed filter, in the traditional design made on the basis of improvement has better features.
Platform: | Size: 26624 | Author: 小令 | Hits:

[VHDL-FPGA-Verilog] DSPBuilderFIR.files

Description: 在信息信号处理过程中，如对信号的过滤、检测、预测等，都要使用滤波器，数字滤波器是数字信号处理（DSP，DigitalSignalProcessing）中使用最广泛的一种器件。常用的滤波器有无限长单位脉冲响应（ⅡR）滤波器和有限长单位脉冲响应（FIR）滤波器两种[1]，其中，FIR滤波器能提供理想的线性相位响应，在整个频带上获得常数群时延从而得到零失真输出信号，同时它可以采用十分简单的算法实现，这两个优点使FIR滤波器成为明智的设计工程师的首选，在采用VHDL或VerilogHDL等硬件描述语言设计数字滤波器时，由于程序的编写往往不能达到良好优化而使滤波器性能表现一般。而采用调试好的IPCore需要向Altera公司购买。笔者采用了一种基于DSPBuilder的FPGA设计方法，使FIR滤波器设计较为简单易行，并能满足设计要求。-err
Platform: | Size: 96256 | Author: yaoming | Hits:

[Other] 66_FIR11

Description: VHDLfir滤波器资料可以实际上一落千丈-VHDLfir filter information can be actually nosedived
Platform: | Size: 7168 | Author: jinlong | Hits:

[VHDL-FPGA-Verilog] autofir

Description: 自适应滤波器设计的仿真程序，完全用C语言编写，可以作为滤波器设计的参考。原为VHDL实验要求的程序。-adaptive filter design simulation program, complete with C language can be used as filter design reference. VHDL to the original requirements of the experimental procedures.
Platform: | Size: 70656 | Author: 李博宁 | Hits:

[VHDL-FPGA-Verilog] DecimationFilterDesignforDDCandImplementingItwithF

Description: 本文介绍了在数字下变频(DDC) 中的抽取滤波器系统设计方法和具体实现方案。采用CIC 滤波器、HB 滤波器、FIR 滤波器三级级联的方式来降低采样率。通过实际验证,证明了设计的可行性-This article describes the digital down conversion (DDC) of the decimation filter system design methods and concrete realization of the program. Using CIC filter, HB filter, FIR filter cascade three-level approach to reduce the sampling rate. Through the actual authentication, to prove the feasibility of the design
Platform: | Size: 468992 | Author: 会飞的鱼 | Hits:

[VHDL-FPGA-Verilog] EDA

Description: 里面是一个FIR滤波器的设计报告里面有具体的代码等等加法器乘法器见发起等等承平-There is a FIR filter design report there are specific code adder multiplier, etc., etc., see Cheng-Ping initiated
Platform: | Size: 189440 | Author: 丛宇 | Hits:

[VHDL-FPGA-Verilog] yl_cic32

Description: 一个三阶梳妆滤波器（CIC）的vhdl的源码-Dressing a third-order filter (CIC) of the VHDL source code
Platform: | Size: 1024 | Author: 白杨 | Hits:

[VHDL-FPGA-Verilog] FIR_verilog

Description: 基于verilog的FIR滤波器，有两种实现方法，分别给出仿真波形-Verilog based on the FIR filter, there are two methods, respectively, the simulation waveform
Platform: | Size: 628736 | Author: yejianchao | Hits:

[VHDL-FPGA-Verilog] DIGTAL_FIR

Description: 环路滤波器的设计，基于FPGA的锁相环应用。-Loop filter design, FPGA-based PLL applications.
Platform: | Size: 774144 | Author: 梁大法 | Hits:

[VHDL-FPGA-Verilog] fir6dlms

Description: lms的verilog代码，我找了好久在才找的的，好东西，大家一起学习-LMS of the Verilog code, I am looking for a long time before looking at the good things we can work together to learn
Platform: | Size: 1024 | Author: 李允 | Hits:

[VHDL-FPGA-Verilog] tdmddc_v61

Description: Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1
Platform: | Size: 54272 | Author: | Hits:

[VHDL-FPGA-Verilog] fir_fpga

Description: 通过VHDL语言进行数字信号处理的FIR操作，可以很好的实现滤波功能，有很好的作用，-Through VHDL languages digital signal processing FIR operation, can good realization filtering, have good role
Platform: | Size: 2135040 | Author: fdf | Hits:

[VHDL-FPGA-Verilog] 6tapFIR

Description: 6阶FIR+verliog+分布式算法（DA）-6 bands FIR+ Verliog+ Distributed Arithmetic (DA)
Platform: | Size: 2048 | Author: zs | Hits:

[VHDL-FPGA-Verilog] fir_Verilog

Description: 用Verilog编写的fir滤波器程序！-Verilog prepared using the procedure fir filter!
Platform: | Size: 5120 | Author: yuming | Hits:

[OS Develop] dds

Description: 这是一个用vhdl语言实现dds的例子，已在quartusII里调通并可以下载到实验箱上，功能正确-This is a use of VHDL language dds example, has been in tune quartusII pass and can be downloaded to the experimental box, the function correctly
Platform: | Size: 331776 | Author: leezhihui | Hits:

[Other] VerilogHDL

Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
Platform: | Size: 79872 | Author: sundan | Hits:

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